1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a memory transistor having a floating gate.
2. Description of the Background Art
Conventionally, in a flash memory, data is written by injecting electrons into a floating gate of a memory transistor and setting a threshold voltage of the memory transistor high (storing data “0”), while data is erased by removing electrons from the floating gate of the memory transistor and setting the threshold voltage of the memory transistor low (storing data “1”).
In such a flash memory, if the erasing condition is weak, it takes longer time to erase data, thereby reducing the operation speed. On the contrary, if the erasing condition is too strong, the threshold voltage is excessively decreased to cause an increased number of depleted memory transistors, thereby resulting in erroneous reading.
There has been proposed a method of preventing depleted memory transistors by reducing a pulse voltage of an erasing pulse in response to a threshold voltage of a memory transistor attaining a verify voltage (Japanese Patent Laying-Open No. 10-228786).
In this erasing method, however, variations in erasing time between chips or memory blocks cannot be reduced. In addition, the erasing time is long.